The present invention relates to a clock generation circuit,a processor system using same, and a clock frequency control method.
In recent years, a low power consumption and long life light emitting diode (LED) has been used more for a lighting system as compared to an incandescent bulb and a fluorescent light. Usually, brightness of the lighting system using such LED (hereinafter referred to as an LED lighting system) can be adjusted by an adjustment lever and a remote control etc. That is, in order to adjust the brightness of LED according to an external control signal, a microcontroller is mounted in the LED lighting system as a processor system provided with a communication function. As a global communication standard of indoor lighting in various institutions etc., DALI (Digital Addressable Lighting Interface) is known. Further, infrared remote controls are often used for the communication in household lighting.
By the way, a reduction in the power consumption of the microcontroller has been required as well. Therefore, the microcontroller is often provided with an operation mode with lower power consumption (hereinafter referred to as a low power consumption mode) than the normal operation mode, such as the standby mode. In the low power consumption mode, a frequency multiplication circuit such as PLL (Phase Locked Loop) stops, and the system operates with a clock signal of a frequency lower than in the normal operation mode. For example, Japanese Unexamined Patent Application Publication No. H10-94019 discloses a data reception apparatus with lower power consumption by reducing the frequency of the clock signal.
On the other hand, in order to maintain the abovementioned communication function, the clock signal for communication (hereinafter referred to as a communication clock signal) needs to maintain the frequency as it is. That is, a clock signal for operating the system (hereinafter referred to as a system clock signal) slows down (switches to a low frequency) with transition to the low power consumption mode. On the other hand, the frequency of the communication clock signal needs to remain constant. In order to synchronize the system clock signal and the communication clock signal, the communication clock signal is generated by dividing the system clock.
Japanese Unexamined Patent Application Publication No. 2004-171487 discloses a technique to maintain the frequency of the clock signal supplied to an LCD (Liquid Crystal Display) controller to be constant in the low power consumption mode by setting the multiple rate to 1/N and then setting the division ratio of a frequency divider provided in a subsequent stage of the PLL to 1/N. Japanese Unexamined Patent Application Publication No. 2004-199135 discloses a technique to divide the system clock that is generated by multiplying the reference clock signal, and generates the clock signal having the same phase and frequency of the reference clock signal. After the multiple rate of the system clock signal is detected, the system clock signal is divided according to the detected multiple rate.